At the present time, the market of electrically erasable and programmable integrated circuit memories is divided in three main memory categories. These are word by word programmable EEPROM memories, page by page programmable EEPROM memories (i.e., where a page includes a plurality of words), and word by word programmable FLASH (or FLASH-EEPROM) memories. Page by page programmable FLASH memories are presently not available for technological reasons which will be quickly understood with reference to FIGS. 1A and 1B. FIG. 1A shows schematically the core of an EEPROM memory, and FIG. 1B shows the core of a FLASH memory. Each memory includes a plurality of memory cells, respectively CEi,j, CFi,j, arranged in an array and connected to word lines WLi and bit lines BLJ.
In FIG. 1A, it can be seen that the cells CEi,j of the EEPROM memory include a floating gate transistor FGT and an access transistor TA. The access transistor TA has its gate G connected to a word line WLi, its drain D connected to a bit line BLj, and its source S connected to the drain D of transistor FGT. Transistor FGT has its gate G coupled to a column selection line CLk by a gate control line CGL and a gate control transistor CGT and its source S connected to a source line SL. The gate of transistor CGT is connected to the word line WLi. Thus, the memory cells CEi,j of a same word line WLi are arranged in columns of k range, and form words Wi,k (generally bytes). These words may be selected when reading by the column selection line CLk and the word line WLi to which they are linked.
In such an EEPROM memory, a programming or erasing operation of a cell includes injecting or extracting electric charges by the Fowler Nordheim effect into or from the floating gate of the transistor FGT of the cell. An erased transistor FGT presents a positive threshold voltage VT1, and a programmed transistor FGT presents a negative threshold voltage VT2. When a reading voltage Vread between VT1 and VT2 is applied to its gate, an erased transistor remains OFF, which corresponds by convention to a logic “0”. A programmed transistor is conductive and corresponds by convention to a logic “1”.
The erasing operation is performed by applying an erasing voltage VPP of about 12 to 20 V to the gate G of transistor FGT while the source line SL is set to ground. The programming operation is performed by applying a programming voltage VPP to the drain D of transistor FGT by the access transistor TA while the gate is set to ground.
With the charge transfers by the Fowler Nordheim effect being performed with a gate current nearly equal to zero, a great number of EEPROM memory cells may be erased or programmed simultaneously. Thus, as indicated above, EEPROM memories are available with page programming that allow, after a collective erasing operation of all the cells of a page (setting them to “0”), simultaneous programming of all the cells of the page which must contain the value “1”. This may be done 256 cells at the same time, for example.
In FIG. 1B, it can be seen that the cells CFi,j of the FLASH memory have a very simple structure and include only one floating gate transistor FGT. Transistor FGT has its gate G connected to a word line WLi, its drain D connected to a bit line BLj, and its source S connected to a source line SL. The source S is sometimes connected to the source line SL by a source transistor (not shown), as described in European Patent Application No. EP704851. The arrangement of the cells of a same word may be progressive or interlaced so that a word Wi,k linked to a line of range i and a column of range k may include eight cells arranged side by side, as represented in FIG. 1B. Or, in the case of interlaced cells, they may be non-adjacent cells. In this case, the physically adjacent cells are generally the same range of cells of the words of a same word line.
In such a FLASH memory, an erasing operation of a cell includes extracting electric charges trapped in the floating gate by the Fowler Nordheim effect. A programming operation includes injecting charges into the floating gate by the “hot electron injection” effect. An erased transistor FGT presents a positive threshold voltage VT1 with a small value, and a programmed transistor presents a threshold voltage VT2 higher than VT1. When a reading voltage Vread between VT1 and VT2 is applied to its gate, an erased transistor is ON, which corresponds by convention to a logic “1”. A programmed transistor remains OFF, which corresponds by convention to a logic “0”.
Because of their simplicity, FLASH memories have the advantage of being very compact in terms of occupied silicon surface. Thus, they present a storing capacity significantly higher than that of EEPROM memories, and they have a lower cost.
On the other hand, FLASH memories have less programming possibilities than EEPROM memories. This is particularly true regarding the possibility of recording simultaneously several words. As a matter of fact, the programming operation of a FLASH cell (by hot electron injection) is performed with a non-negligible current by applying to the cell transistor FGT a drain voltage of about 6 V and a gate voltage of about 12 V. The transistor FGT is in the ON state and highly biased during the operation.
Thus, if all the cells of a same sector in FLASH memories are frequently erased simultaneously (a sector comprising several word lines), the simultaneous programming of a great number of FLASH cells is, on the other hand, impossible due to the significant current collected in the source lines SL. This current is capable of destroying the metal tracks connecting the transistors of the memory and/or the connections between the tracks of different levels. In practice, the number of cells which can be simultaneously programmed is generally limited to eight. Thus, a FLASH memory cannot allow the simultaneous recording of several words, and it always operates in the “word by word” programming mode.
Although this drawback is offset by a very short programming time, in the order of microseconds as opposed to milliseconds for an EEPROM memory, the recording of a series of words into a FLASH memory requires sending a programming instruction for each recorded word. Conversely, a page by page programmable EEPROM memory requires one programming instruction only, followed by the series of the words to be recorded. The words are stored in a locked latch with a parallel output and are recorded simultaneously into the EEPROM memory in a single step.
Finally, there exist a lot of electronic circuits (e.g., microprocessor cards, micro-computer cards, sound cards, graphic cards, and the like) which include page by page programming EEPROM memories. These electronic circuits cannot operate with FLASH memories because their data transfer protocol is not compatible with such memories.
A FLASH memory including a writing protection device and a programming buffer circuit is disclosed in French Patent No. FR 2 756 410. This memory includes a plurality of high voltage registers in parallel connected to the bit lines of the memory, where each register is provided for storing a word. The structure of such memory allows the imitation of the page mode of EEPROM memories while keeping a word by word programming mode. However, such a memory including a plurality of high voltage registers is relatively complex to design and is suitable for limited applications only.